The performance of many digital systems is limited by the interconnection bandwidth between chips, boards, and cabinets. As VLSI technology continues to scale, system bandwidth will become an even more significant bottleneck as the number of I/Os scales more slowly than the bandwidth demands of on-chip logic. Also, off-chip signalling rates have historically scaled more slowly than on-chip clock rates. Most digital systems today use full-swing unterminated signalling methods that are unsuited for data rates over 100 MHz on one meter wires. Even good current-mode signalling methods with matched terminations and carefully controlled line and connector impedance are limited to about 1 GHz by the frequency-dependent attenuation of copper lines. Without new approaches to high-speed signalling, bandwidth will stop scaling with technology when we reach these limits.